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1. product pro?le 1.1 general description n-channel enhancement mode ?eld-effect power transistor in a plastic package using philips high-performance automotive (hpa) trenchmos? technology, featuring very low on-state resistance. 1.2 features 1.3 applications 1.4 quick reference data 2. pinning information [1] it is not possible to make a connection to pin 2 of the sot404 package. buk95/96/9e06-55b n-channel trenchmos? logic level fet rev. 03 30 november 2004 product data sheet n trenchmos? technology n q101 compliant n 175 c rated n logic level compatible. n automotive systems n 12 v and 24 v loads n motors, lamps and solenoids n general purpose power switching. n e ds(al)s 679 mj n r dson = 5.1 m w (typ) n i d 75 a n p tot 258 w. table 1: pinning pin description simpli?ed outline symbol 1 gate (g) sot78 (to-220ab) sot404 (d 2 -pak) sot226 (i 2 -pak) 2 drain (d) [1] 3 source (s) mb mounting base; connected to drain (d) 12 mb 3 13 2 mb 12 mb 3 s d g mbb076
9397 750 13519 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 30 november 2004 2 of 15 philips semiconductors buk95/96/9e06-55b n-channel trenchmos? logic level fet 3. ordering information 4. limiting values [1] current is limited by power dissipation chip rating [2] continuous current is limited by package table 2: ordering information type number package name description version BUK9506-55B to-220ab plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead to-220ab sot78 buk9606-55b d 2 -pak plastic single-ended surface mounted package (philips version of d 2 -pak); 3 leads (one lead cropped) sot404 buk9e06-55b i 2 -pak plastic single-ended package (philips version of i 2 -pak); low-pro?le 3 lead to-220ab sot226 table 3: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v ds drain-source voltage (dc) - 55 v v dgr drain-gate voltage (dc) r gs =20k w -55v v gs gate-source voltage (dc) - 15 v i d drain current (dc) t mb =25 c; v gs =5v; figure 2 and 3 [1] - 146 a [2] -75a t mb = 100 c; v gs =5v; figure 2 [2] -75a i dm peak drain current t mb =25 c; pulsed; t p 10 m s; figure 3 - 587 a p tot total power dissipation t mb =25 c; figure 1 - 258 w t stg storage temperature - 55 +175 c t j junction temperature - 55 +175 c source-drain diode i dr reverse drain current (dc) t mb =25 c [1] - 146 a [2] -75a i drm peak reverse drain current t mb =25 c; pulsed; t p 10 m s - 587 a avalanche ruggedness e ds(al)s non-repetitive drain-source avalanche energy unclamped inductive load; i d =75a; v ds 55 v; r gs =50 w ; v gs = 5 v; starting at t j =25 c - 679 mj
9397 750 13519 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 30 november 2004 3 of 15 philips semiconductors buk95/96/9e06-55b n-channel trenchmos? logic level fet v gs 3 5v fig 1. normalized total power dissipation as a function of mounting base temperature. fig 2. continuous drain current as a function of mounting base temperature. t mb =25 c; i dm is single pulse. fig 3. safe operating area; continuous and peak drain currents as a function of drain-source voltage. 03aa16 0 40 80 120 0 50 100 150 200 t mb ( c) p der (%) 03nh85 0 50 100 150 0 50 100 150 200 t mb ( c) i d (a) capped at 75 a due to package p der p tot p tot 25 c () ----------------------- 100 % = 03nh83 1 10 10 2 10 3 10 -1 1 10 10 2 v ds (v) i d (a) dc 100 ms 10 ms limit r dson = v ds / i d 1 ms t p = 10 m s 100 m s capped at 75 a due to package
9397 750 13519 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 30 november 2004 4 of 15 philips semiconductors buk95/96/9e06-55b n-channel trenchmos? logic level fet 5. thermal characteristics 5.1 transient thermal impedance table 4: thermal characteristics symbol parameter conditions min typ max unit r th(j-mb) thermal resistance from junction to mounting base figure 4 - - 0.58 k/w r th(j-a) thermal resistance from junction to ambient sot78 (to-220ab) and sot226 (i 2 -pak) vertical in free air - 60 - k/w sot404 (d 2 -pak) mounted on a printed-circuit board; minimum footprint; vertical in still air - 50 - k/w fig 4. transient thermal impedance from junction to mounting base as a function of pulse duration. 03nh84 single shot 0.2 0.1 0.05 0.02 10 -3 10 -2 10 -1 1 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 1 t p (s) z th(j-mb) (k/w) d = 0.5 t p t p t t p t d =
9397 750 13519 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 30 november 2004 5 of 15 philips semiconductors buk95/96/9e06-55b n-channel trenchmos? logic level fet 6. characteristics table 5: characteristics t j =25 c unless otherwise speci?ed. symbol parameter conditions min typ max unit static characteristics v (br)dss drain-source breakdown voltage i d = 250 m a; v gs =0v t j =25 c 55--v t j = - 55 c 50--v v gs(th) gate-source threshold voltage i d = 1 ma; v ds =v gs ; figure 9 and 10 t j =25 c 1.1 1.5 2 v t j = 175 c 0.5 - - v t j = - 55 c - - 2.3 v i dss drain-source leakage current v ds =55v; v gs =0v t j =25 c - 0.02 1 m a t j = 175 c - - 500 m a i gss gate-source leakage current v gs = 15 v; v ds = 0 v - 2 100 na r dson drain-source on-state resistance v gs =5v; i d =25a; figure 6 and 8 t j =25 c - 5.1 6.0 m w t j = 175 c --12m w v gs = 4.5 v; i d =25a; figure 6 and 8 - - 6.4 m w v gs = 10 v; i d =25a; figure 6 and 8 - 4.8 5.4 m w dynamic characteristics q g(tot) total gate charge i d = 25 a; v dd =44v; v gs =5v; figure 14 and 16 -60-nc q gs gate-source charge - 11 - nc q gd gate-drain (miller) charge - 22 - nc v plat plateau voltage - 2.4 - v c iss input capacitance v gs =0v; v ds = 25 v; f = 1 mhz; figure 12 - 5 674 7565 pf c oss output capacitance - 755 906 pf c rss reverse transfer capacitance - 255 350 pf t d(on) turn-on delay time v ds =30v; r l = 1.2 w ; v gs =5v;r g =10 w -37-ns t r rise time -95-ns t d(off) turn-off delay time - 117 - ns t f fall time - 106 - ns l d internal drain inductance from drain lead 6 mm from package to center of die - 4.5 - nh from contact screw on mounting base to center of die sot78 - 3.5 - nh from upper edge of drain mounting base to center of die sot404/sot226 - 2.5 - nh l s internal source inductance from source lead to source bonding pad - 7.5 - nh
9397 750 13519 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 30 november 2004 6 of 15 philips semiconductors buk95/96/9e06-55b n-channel trenchmos? logic level fet source-drain diode v sd source-drain (diode forward) voltage i s = 25 a; v gs =0v; figure 15 - 0.85 1.2 v t rr reverse recovery time i s = 20 a; di s /dt = - 100 a/ m s; v gs =0v;v r =30v -64-ns q r recovered charge - 79 - nc table 5: characteristics t j =25 c unless otherwise speci?ed. symbol parameter conditions min typ max unit t j =25 ct j =25 c; i d =25a fig 5. output characteristics: drain current as a function of drain-source voltage; typical values. fig 6. drain-source on-state resistance as a function of gate-source voltage; typical values. t j =25 c fig 7. drain-source on-state resistance as a function of drain current; typical values. fig 8. normalized drain-source on-state resistance factor as a function of junction temperature. 03nj65 0 50 100 150 200 250 300 350 0246810 v ds (v) i d (a) 3.8 3.6 3.4 3.2 3 2.8 2.6 2.4 10 6 4 4.2 5 v gs (v) is 03nj64 4 5 6 7 3 7 11 15 v gs (v) r dson (m w ) 03nj66 2 4 6 8 10 12 14 0 100 200 300 400 i d (a) r dson (m w ) v gs (v) is 3 3.2 10 5 4 3.4 03ne89 0 0.5 1 1.5 2 -60 0 60 120 180 t j ( c) a a r dson r dson 25 c () ---------------------------- - =
9397 750 13519 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 30 november 2004 7 of 15 philips semiconductors buk95/96/9e06-55b n-channel trenchmos? logic level fet i d = 1 ma; v ds =v gs t j =25 c; v ds =v gs fig 9. gate-source threshold voltage as a function of junction temperature. fig 10. sub-threshold drain current as a function of gate-source voltage. t j =25 c; v ds =25v v gs = 0 v; f = 1 mhz fig 11. forward transconductance as a function of drain current; typical values. fig 12. input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. 03ng52 0.0 0.5 1.0 1.5 2.0 2.5 -60 0 60 120 180 t j ( c) v gs(th) (v) max typ min 03ng53 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 0123 v gs (v) i d (a) max typ min 03nj62 0 50 100 150 200 0 20406080 i d (a) g fs (s) 03nj67 0 2000 4000 6000 8000 10 -1 1 10 10 2 v ds (v) c (pf) c iss c oss c rss
9397 750 13519 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 30 november 2004 8 of 15 philips semiconductors buk95/96/9e06-55b n-channel trenchmos? logic level fet v ds =25v t j =25 c; i d =25a fig 13. transfer characteristics: drain current as a function of gate-source voltage; typical values. fig 14. gate-source voltage as a function of gate charge; typical values. v gs =0v fig 15. source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. fig 16. gate charge waveform de?nitions. 03nj63 0 25 50 75 100 0123 v gs (v) i d (a) t j = 175 c t j = 25 c 03nj61 0 1 2 3 4 5 0 204060 q g (nc) v gs (v) v dd = 14 v v dd = 44 v 03nj60 0 25 50 75 100 0.0 0.2 0.4 0.6 0.8 1.0 v sd (v) i s (a) t j = 175 c t j = 25 c 003aaa508 v gs v gs(th) q gs1 q gs2 q gd v ds q g(tot) i d q gs v plat
9397 750 13519 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 30 november 2004 9 of 15 philips semiconductors buk95/96/9e06-55b n-channel trenchmos? logic level fet 7. package outline fig 17. package outline sot78 (to-220ab). references outline version european projection issue date iec jedec jeita sot78 sc-46 3-lead to-220ab d d 1 q p l 123 l 1 (1) b 1 e e b 0 5 10 mm scale plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead to-220ab sot78 dimensions (mm are the original dimensions) a e a 1 c note 1. terminals in this zone are not tinned. q l 2 unit a 1 b 1 d 1 e p mm 2.54 qq a b d c l 2 max. 3.0 3.8 3.6 15.0 13.5 3.30 2.79 3.0 2.7 2.6 2.2 0.7 0.4 15.8 15.2 0.9 0.6 1.3 1.0 4.5 4.1 1.39 1.27 6.4 5.9 10.3 9.7 l 1 (1) e l 01-02-16 03-01-22 mounting base
9397 750 13519 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 30 november 2004 10 of 15 philips semiconductors buk95/96/9e06-55b n-channel trenchmos? logic level fet fig 18. package outline sot404 (d 2 -pak). unit a references outline version european projection issue date iec jedec jeita mm a 1 d 1 d max. e el p h d q c 2.54 2.60 2.20 15.80 14.80 2.90 2.10 11 1.60 1.20 10.30 9.70 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 b dimensions (mm are the original dimensions) sot404 0 2.5 5 mm scale plastic single-ended surface mounted package (d 2 -pak); 3 leads (one lead cropped) sot404 e e e b d 1 h d d q l p c a 1 a 13 2 mounting base 01-02-12 04-10-13
philips semiconductors buk95/96/9e06-55b n-channel trenchmos? logic level fet 9397 750 13519 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 30 november 2004 11 of 15 fig 19. package outline sot226 (i 2 -pak). references outline version european projection issue date iec jedec jeita sot226 low-profile 3-lead to-220ab d d 1 l 123 l 2 l 1 mounting base b 1 e e q b 05 10 mm scale plastic single-ended package (philips version of i 2 -pak); low-profile 3 lead to-220ab sot226 dimensions (mm are the original dimensions) a e a 1 c note 1. terminals in this zone are not tinned. unit a 1 b 1 d 1 eq mm 2.54 l 1 2.6 2.2 3.30 2.79 15.0 13.5 10.3 9.7 1.6 1.2 11 0.7 0.4 1.3 1.0 0.85 0.60 1.40 1.27 4.5 4.1 ab d max c 3 l 2 (1) max e l 03-10-14 04-02-24
9397 750 13519 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 30 november 2004 12 of 15 philips semiconductors buk95/96/9e06-55b n-channel trenchmos? logic level fet 8. mounting dimensions in mm. fig 20. re?ow soldering footprint for sot404. msd057 solder lands solder resist occupied area solder paste 10.50 7.40 7.50 1.50 1.70 10.60 1.20 1.30 1.55 5.08 10.85 0.30 2.15 8.35 2.25 4.60 0.20 3.00 4.85 7.95 8.15 8.075 8.275 5.40 1.50
9397 750 13519 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 30 november 2004 13 of 15 philips semiconductors buk95/96/9e06-55b n-channel trenchmos? logic level fet 9. revision history table 6: revision history document id release date data sheet status change notice doc number supersedes buk95_96_9e06_55b_3 20041130 product data sheet - 9397 750 13519 buk95_96_9e06_55b_2 modi?cations: ? the format of this data sheet has been redesigned to comply with the new presentation and information standard of philips semiconductors. ? latest version of package outlines imported into section 7 of data sheet. buk95_96_9e06_55b-02 20021010 product data sheet - 9397 750 10474 buk95_96_9e06_55b-01 buk95_96_9e06_55b-01 20020813 product data sheet - 9397 750 09946 -
philips semiconductors buk95/96/9e06-55b n-channel trenchmos? logic level fet 9397 750 13519 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 30 november 2004 14 of 15 10. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 11. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 12. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 13. trademarks trenchmos is a trademark of koninklijke philips electronics n.v. 14. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2004 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 30 november 2004 document number: 9397 750 13519 published in the netherlands philips semiconductors buk95/96/9e06-55b n-channel trenchmos? logic level fet 15. contents 1 product pro?le . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 general description. . . . . . . . . . . . . . . . . . . . . . 1 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 quick reference data. . . . . . . . . . . . . . . . . . . . . 1 2 pinning information . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 thermal characteristics. . . . . . . . . . . . . . . . . . . 4 5.1 transient thermal impedance . . . . . . . . . . . . . . 4 6 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 mounting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 10 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 14 11 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 12 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 13 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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